1. Field of the Invention
The present invention relates to a clock signal modeling circuit, and particularly to an improved clock signal modeling circuit capable of more quickly generating an internal clock signal from an external clock signal without using a phase locked loop (PLL) and a delay locked loop (DLL).
2. Description of the Conventional Art
Recently, memory chips which operate at a high speed have been developed. However, in order that a certain circuit may generate an internal clock signal, it is necessary to receive an external clock signal and have a certain delay process. In this regard, since the delay process has its limit, there is a certain limit to reduce the clock access time until the external clock signal is received and the data stored in a memory is outputted.
Therefore, generally, a PLL or a DLL are used in order to reduce the clock access time, so that delay between the external clock signal and the internal clock signal can be reduced, and it is possible to more quickly generate the internal clock signal than that of the external clock signal.
However, a method of reducing a clock access time using the PLL and DLL requires hundreds of clock cycles, and even in a stand-by state the PLL and DLL should be operated, so that more current consumption is disadvantageously required.
In addition, if the PLL or DLL is turned off in order to reduce the current consumption in a self refresh operation which does not access a chip, in order to access the chip again, it is required to stop the operation of the self refresh operation, and the PLL and DLL should be operated, so that it is difficult to lock an external clock signal and an internal clock signal for hundreds of cycles.